This invention relates to an MOS semiconductor device, and more particularly to an MOS semiconductor device having a short channel and a method of manufacturing the same.
In recent years, noticeable development has been made in the high integration of an electric circuit, resulting in the extreme miniaturization of circuit elements. The miniaturization of circuit elements is indeed useful for the high speed operation of a semiconductor device. However, the more advanced the miniaturization, the more adversely affected the property of the semiconductor device. For example, with an MOS transistor having a short channel, impression of a drain voltage tends to give rise to a punch-through effect in a region defined between the source and drain of a transistor. This event deteriorates the drain current-gate voltage characteristics in a subthreshold range. In other words, the short channel type MOS transistor has the drawback that a punch-through current readily flows through the MOS transistor, thereby obstructing the complete pinch-off of the drain current. Such occurrence leads to the difficulty that, for example, in an MOS dynamic RAM (random access memory), data stored in the form of an electric charge tends to leak.
To suppress leakage current resulting from the punch-through effect arising in the above-mentioned short channel type MOS transistor, the conventional process comprises providing a layer of a high impurity concentration in the deep portion of the channel region. However, the provision of such a deeply embedded impurity layer at high concentration gives rises to an increase in the threshold voltage of the resultant MOS device. Further, the threshold voltage is largely governed by a bias voltage impressed on a substrate, presenting difficulties in designing an integrated circuit for an MOS semiconductor device.